a. Field of the Invention
The invention relates to high speed transistor switching circuits, and more particularly to a high speed transistor switching circuit for use in switching very low currents of the type found in integrated circuit digital to analog converters and the like.
B. Prior Art
High speed transistor switching circuits for switching low levels of current have many applications, one of which is in the field of digital to analog converters. In such converters, it is desirable to produce an analog output from a digitally coded signal. Such a digitally coded signal usually appears as a digital word formed by a number of "bits", which are typically one's and zero's. Digital to analog converters (DAC) for achieving this are well-known in the prior art, and the theory of operation for such circuits, hereafter referred to as DACs, are described in the book "Analog Integrated Circuit Design", by A. B. Grebene, Van Nostrand, 1972, p. 328-350, incorporated by reference herein.
In the above-mentioned book, the author points out that the transfer function of a DAC can be written as follows: EQU A = P[b.sub.1 2.sup.-1 + b.sub.2 2.sup.-2 + . . . + b.sub.N 2.sup.-N ]
the implementation of the DAC contains four separate parts including a reference signal corresponding to the parameter P in the above equation; a set of binary switches to simulate the binary coefficients, b.sub.1 , b.sub.2 , . . . b.sub.n ; a resistive weighting network which provides the factors 2.sup.-1 through 2.sup.-N, and an output summing line for forming the output of the apparatus, A.
A simplified apparatus for carrying out a DAC system is shown in FIG. 1 of the drawings. In FIG. 1, a series of resistors serve to decrement a reference current supplied by the reference source, V.sub.REF, as such current is available along line 11. In FIG. 1, the decrementing resistors are labeled R, 2R, 4R, . . . 2.sup.(N-1) R. Thus, twice as much current flows through branch 12 than branch 13. Twice as much current flows through branch 13 as flows through branch 14 and so on. Of course, current will flow toward the output terminal O, in line 16, only if a respective current switch is moved to its nongrounded position, opposite that shown in the figure.
To limit the spread in the value of resistors, networks have been devised which limit the spread of resistor values, yet achieve binary weighting of currents. One such network is known as a R-2R ladder network, discussed in the above mentioned book. An improved electrical ladder network is the subject of my copending patent application entitled "Multi-Stage Electrical Ladder for Decrementing a Signal Into a Plurality of Weighted Signals", Ser. No. 642,770, filed Dec. 22, 1975.
The switches S1, S2, S3, . . . SN are usually high speed current switches. Such switches of the prior art may be seen in U.S. Pat. Nos. 3,747,088 and 3,842,412.
A more advanced prior art switch is shown in FIGS. 2 and 3 of the drawings.
FIG. 1 of the drawings shows switches S1, S2, S3, SN for use in a simplified digital to analog converter where input currents supplied along line 11 by the source of V.sub.REF is decremented in lines 12, 13, 14, 15 by the respective resistors R, 2R, 4R, 2.sup.(N-1) R. Digital input signals are supplied to the switches S1, S2, S3, SN and determine the position of the switches for forming an analog signal which is supplied to the amplifier 17 and then to the output O.
FIG. 2 shows a prior art circuit which was described in an article entitled "A Complete Monolithic 10-b D/A Converter" by D. Dooley, appearing in IEEE Journal of Solid State Circuits, December 1973. In the circuit of FIG. 2, the transistors Q21, Q22, Q23, Q24, Q26 and Q27 form an emitter coupled logic gate which is Schottky clamped by the Schottky diodes D21, D22 for directing steering current between circuit branches wherein the transistors Q26, Q27 are situated. The transistors Q26, Q27 supply steering current to a mutually connected node A which is pulled by the current source 28 which is part of a ladder network indicated by the dashed line 29. Resistors R and 2R form extensions and rungs, respectively, of such a ladder network, for example of the R-2R type discussed in the book by Grebene, supra, p. 333.
Transistors Q26 and Q27 draw current from two different locations. Q26 draws current from digital ground, while Q27 draws current from a sum line 30. Thus, the current pulled by transistor Q28 from node A comes either from ground or from the output summing line 30, depending on the logic input signal which controls the balance of the network formed by transistors Q21, Q22, Q23, Q24.
Another prior art circuit having the same use as the circuit of FIG. 2, is shown in FIG. 3. In this circuit, a two-branched input is formed by the input transistors Q32, Q33. The input to transistor Q32 is a logic input signal which controls the balance of flow of current from the transistor Q31. The input to transistor Q33 is a logic reference signal which sets the threshold at which the circuit becomes unbalanced, allowing a logic input signal to change the balance of current flow from one branch of the circuit to the other. Current is thereby steered between the transistors Q34 and Q35, pulling current either from the sum line 40 or from digital ground 41. Transistors Q34, Q35 have emitters connected to the common node A' which supplies current pulled by transistor Q36, a current source within the ladder network indicated by the dashed line 39. The resistor R3, connected to transistor Q36 is a resistor in the ladder network and may be one of the resistors in an R-2R network. A more detailed description of the operation of the circuit of FIG. 3 is contained in a paper entitled "An Integrated Circuit 12-Bit D/A Converter" by Robert B. Craven, published in the 1975 IEEE International Solid-State Circuits Conference, Feb. 12, 1975, p. 40. Another well known circuit of the prior art is an integrated circuit known as Motorola MC1508 which is described in a data sheet published by Motorola, Inc., Phoenix, Arizona.
One of the problems present in prior art circuits is that only a single ended output is available, usually the sum line 30 as in FIG. 2 or the sum line 40, as in FIG. 3. In many applications there is a need not only for a summing current, I.sub.OUT , but for a complementary current, I.sub.OUT. Moreover, prior art switches are not able to switch very low current levels at high speed because of the need to charge parasitic capacitance and the influence of transient signals within the circuit. Another problem with circuits of the prior art is that output compliance is not possible and that logic thresholds are not fully adjustable.
It is therefore an object of the invention to devise a high speed, low current switching circuit with complementary true current outputs, i.e. high impedance outputs, and having high output voltage compliance, with an adjustable logic threshold. Such voltage compliance should be wide enough to allow output levels which may swing above the positive power supply.